Memory Disaggregation with CXL: Opportunities and Challenges
Abstract:
Memory disaggregation is an emerging paradigm that decouples memory from the traditional memory bus, enabling compute and memory resources to scale independently. By allowing processors across multiple hosts to share a common memory pool, this architecture improves utilization, reduces cost, and boosts the performance of memory-intensive workloads. Compute Express Link (CXL), an open-standard interconnect over PCIe, provides the foundation for this vision by preserving the familiar byte-addressable, load-store programming model while extending cache coherence across host memory, device memory, and other byte-addressable devices. While early deployments of CXL have demonstrated promising results for memory scaling, significant challenges remain before the full potential of CXL-based memory disaggregation can be realized. In this talk, I will highlight both the opportunities and the obstacles in this space. I will present our recent and ongoing work on managing disaggregated memory, examining the architectural implications of combining local and disaggregated memory tiers, and exploring software-based coherence mechanisms to ensure memory consistency across isolated address spaces without hardware coherence — an early step toward enabling future CXL-based cross-host data sharing.
Bio:
Dr. Jia Rao is currently an Associate Professor in the Department of Computer Science and Engineering at the University of Texas at Arlington. His research lies broadly in the areas of Operating Systems, Parallel and Distributed Computing, and Cloud Computing. His recent focus is on performance optimization and system support for emerging hardware devices and machine learning workloads. His work has been published in prestigious conferences, including SOSP, OSDI, EuroSys, USENIX ATC, HPCA, Supercomputing, PPoPP, HPDC, SoCC, ICDCS, and IPDPS. Highlights of Dr. Rao's research include a National Science Foundation (NSF) CAREER award, best paper awards at Middleware (2021), APSys (2016), ICAC (2013), and best paper nominations at HPCA (2013) and HPDC (2013). Dr. Jia Rao received his B.S. and M.S. degrees in Computer Science from Wuhan University in 2004 and 2006, respectively, and a Ph.D. degree in Computer Engineering from Wayne State University in 2011.