Design space exploration towards energy efficient Coarse Grained Reconfigurable Arrays
Dr Peh Li Shiuan, Provost'S Chair Professor, School of Computing
COM3 Level 2
SR21, COM3 02-60
Abstract:
Coarse-Grained Reconfigurable Architectures (CGRAs) offer a strong performance, energy efficiency, and adaptability. However, with the rise of more demanding applications, particularly on edge devices, there is a continuous demand for better energy efficiency to extend battery life.
This thesis explores inefficiencies in state-of-the-art CGRA architectures and proposes techniques to improve energy efficiency by mitigating those inefficiencies.
Firstly, most CGRAs adhere to a uniform structure with a homogeneous set of resources which leads to substantial idle resources while mapping irregular applications and creates inefficiency. This thesis proposes REVAMP, an automated design space exploration framework that helps architects uncover and add heterogeneity to a diverse range of originally homogeneous CGRAs when fed with a suite of target applications. REVAMP explores a comprehensive set of optimizations, thereby converting a uniform CGRA into a more irregular architecture with improved energy efficiency.
Secondly, CGRAs follow a rigid execution model --- either spatio-temporal or spatial --- irrespective of the workload, limiting their efficiency. Spatio-temporal execution increases energy consumption while spatial execution affects the performance of complex applications. This thesis introduces FLEX, a CGRA with a novel, flexible spatio-temporal vector dataflow execution model. The model processes a vector of data sequentially and chains them spatio-temporally. FLEX also supports variable vector lengths determined at compile time, enabling a more flexible execution paradigm delivering improved efficiency.
Third, coarser granularity of CGRAs impact the performance in applications that require adaptive precision computations, leading to reduced resource utilization and potentially affecting overall efficiency. This thesis proposes ADAPT, a hardware-software co-design methodology developed to enable arbitrary precision computations on CGRAs. The software mapper in ADAPT handles the precision variations at dataflow graph stage by converting variable precision DFG to a uniform lower-precision (8-bit) DFG using arithmetic transformations. This allow the ADAPT hardware microarchitecture to be simplified and sliced to comprise only lower-precision (8-bit) functional units interconnected with lower-precision (8-bit) parallel NoCs, which can be configured to handle precision variations within and among applications efficiently.
Finally, the thesis details PACE, a SoC designed with a RISC-V processor and a CGRA as the primary accelerator, targeting low-power computations for edge systems.