Toward General-Purpose Dynamic Dataflow Processing

Abstract:

Advancements in compute-intensive technologies such as Artificial Intelligence (AI), Virtual Reality (VR), and the Internet of Things (IoT) demand high performance in energy-efficient environments, encompassing both mobile devices and data centers. Traditional Central Processing Units (CPUs), constrained by incremental performance improvements, face challenges in meeting these evolving requirements. Spacial architectures like Coarse-Grained Reconfigurable Architectures (CGRAs) provide an efficient and flexible alternative, yet their on-chip network's limited connectivity complicates optimal component placement and routing, resulting in extended scheduling times for dataflow graphs.

In response to these challenges, our research introduces an ultra-fast CGRA compilation method, significantly reducing scheduling time through the use of single-cycle multi-hop data transfer. We also develop 3DRA, a new dataflow-style architecture that enhances the usability and efficiency of CGRAs, offering fast programmability from input dataflow graphs and dynamic run-time adaptation. Furthermore, we present GraphWave, a vertex-centric graph accelerator, which applies 3DRA style data driven execution in graph processing while targeting larger and more diverse computing tasks. Additionally, our ongoing work focuses on a new hierarchical network design that aims to enhance the performance, efficiency, and scalability of 3DRA.

Our research provides innovative solutions to the challenges posed by modern compute-intensive applications, delivering efficient and flexible architectures that cater to the growing demand for high-performance computing in energy-sensitive environments.