Software-defined Time-Predictable Many-core Architecture for LTE Baseband Processing
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Abstract:
Wireless communication standards such as Long Term Evolution (LTE) are rapidly changing to support the high data-rate of wireless-enabled devices. The physical layer baseband processing has strict real-time deadlines, with 5G expected to achieve 10x throughput improvement, 100 billion connections and handle multiple service categories. Existing base station transceivers utilizing customized DSP cores or fixed-function hardware accelerators incur significant Non-Recurring Engineering costs while software programmable many-core architectures are unable to provide performance guarantees due to unpredictable timing. In this thesis, we design scalable lightweight hardware (with timing predictability) that can be programmed and defined by sophisticated software mechanisms to achieve performance requirements at low-power. In this regard, we propose a predictable, software-defined many-core architecture that exploits the massive parallelism of the LTE/5G baseband processing workload. The idea is to employ hundreds of programmable lightweight in-order cores, per-core software-controlled Scratchpad Memory (SPM) and a purely software-scheduled bufferless Network-On-Chip (NoC). This architecture is supported by a run-time scheduler and a software tool-chain that automates data mapping in SPM as well as NoC communication for the baseband processing workload. We show that the proposed architecture meets the performance requirements of LTE/5G baseband processing with significantly lower average power than contemporary platforms.