Architecture Designs for Energy-Efficient and Adaptable STTRAM Cache Hierarchies
COM1 Level 3
MR1, COM1-03-19
Abstract:
The Spin-Transfer Torque RAM (STTRAM) is a non-volatile memory (NVM) technology that has emerged as promising alternative to traditional SRAMs in cache architectures for a broad range of computer systems, including mobile devices, embedded systems, desktop computers, cloud computers, etc. STTRAMs offer advantages of non-volatility, low leakage power, fast read speed, high endurance, and high density, which makes them especially attractive for resource-constrained devices. STTRAMs, however, also have some significant drawbacks, such as high write latency and energy, which may result in overheads for resource-constrained devices. In addition to changing user quality of experience expectations, applications typically have dynamic runtime cache resource requirements due to variable execution characteristics, necessitating cache architectures that can be adapted to the applications' variable needs.
In this talk, I will discuss some techniques we have explored for enabling adaptability in STTRAM cache hierarchies. Specifically, I will focus on the idea of logically adaptable retention time STTRAM (LARS) and highly adaptable last level STTRAM (HALLS) caches for improving the cache hierarchy's energy consumption, without introducing substantial overheads.
Biodata:
Tosiron Adegbija is an Assistant Professor of Electrical and Computer Engineering at the University of Arizona, USA. His research interests are in computer architecture, with an emphasis on adaptable computing, memory subsystems, low-power embedded systems design and optimization methodologies, and processor optimizations for the Internet of Things (IoT). Tosiron received his PhD in Electrical and Computer Engineering from the University of Florida in 2015. He was a recipient of the CAREER Award from the National Science Foundation in 2019. More about his research activities and publications can be found at www.tosiron.com.