Intelligent Network-on-Chip Algorithm Designs and Hardware Applications
COM2 Level 4
Executive Classroom, COM2-04-02
Abstract:
The NoC has been proven as an efficient way to solve the complex on-chip communication issues in multicore system. In recent years, the three-dimensional stacking dies further improve the integration density of the chip and leverage the 3D NoC development. However, the high integration density of the stacking dies results in large power density at high operation frequency. Besides, the unequal thermal conductance of different logic layer s leads the 3D NoC to face a much severer thermal problem than 2D NoC. Those thermal issues may limit the performance gain of 3D integration and cause lower reliability of the 3D NoC designs. In the first part of this talk, I will present some design methodologies for thermal-aware 3D NoC which are developed in the recent years. On the other hand, with the powerful computing resource in the multicore system, it facilitates the machine learning (or neural network) engine design in the edge computing in the recent two years. However, due to the intensive computation and communication among each neuron of the neural network, the interconnection between each neuron become too complicated to ANN hardware accelerator design. Hence, the research of the NoC-based neural network hardware design attracts much attention recently. In the second part of this talk, I will introduce my current project about reconfigurable NoC-based neural network design and share you some results of this research topics.
Biodata:
Kun-Chih (Jimmy) Chen received his PhD degree from Nation Taiwan University, Taiwan, in Graduate Institute of Electronics Engineering in 2013. From October 2014 to January 2015, he served as a postdoctoral fellow in Intel NTU Connected Context Computing Center working on the development of Green Sensing Platform for Internet of Things (IoTs), Reliable Thermoelectric Converter, and Power-aware Software Defined Network (SDN). From February 2015 to July 2016, Dr. Chen joined the faculty of Electronic Engineering Department of Feng Chia University. He is currently an Assistant Professor of Computer Science and Engineering Department of National Sun Yat-Sen University. His research interests include Multiprocessor SoC (MPSoC) design, Neural network learning algorithm design, Reliable system design, and VLSI/CAD design. Dr. Chen served as Technical Program Committee (TPC) Chair of the International Workshop on Network on Chip Architectures (NoCArc 2018), General Chair of the International Workshop on Network on Chip Architectures (NoCArc 2019) and Guest Editor of Journal of Systems Architecture (JSA) and Nano Communication Network (NanoComNet). Besides, he also served as the technical program committee of some major IEEE international conferences, such as ISCAS and SOCC. Dr. Chen received the Best Paper Award of International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2014), the Best Paper Award of International Joint Conference on Convergence (IJCC 2016), and the Best PhD Dissertation Award of IEEE Taipei Section in 2014. Besides, Dr. Chen also receive NSYSU New Faculty Award (3 times), NSYSU-CSE Excellent Tutor Award, and NSYSU Excellent Teaching Award. He is a member of IEEE.