DRAM Caches for Low Latency
14 Aug 2019 Wednesday, 10:30 AM to 12:00 PM
COM2 Level 4
Executive Classroom, COM2-04-02
DRAM caches have emerged as a potent solution for bandwidth-hungry workloads. It is widely believed, however, that DRAM caches are not useful in lowering the average memory access time (AMAT) in workloads that are not bandwidth-constrained. In this talk, I will argue otherwise by describing two applications of DRAM caches for AMAT reduction. The first of these is in relieving the NUMA bottleneck in multi-socket systems by eliminating high-latency accesses to the remote socket(s). The second application is in replacing shared on-chip last-level caches with private DRAM caches -- a radical, technology-scalable alternative to today's multicore cache hierarchies that enables high cache capacity at low access latency.
Boris Grot is an Associate Professor in the School of Informatics at the University of Edinburgh. His research seeks to address efficiency bottlenecks and capability shortcomings of processing platforms for data-intensive applications. Boris is a member of the MICRO Hall of Fame, and several of his publications have been recognized with awards, including an IEEE Micro Top Pick and the Best Paper Award at HPCA 2019. Boris holds a PhD in Computer Science from The University of Texas at Austin. Prior to starting at Edinburgh, he spent two years as a post-doctoral researcher at EPFL.