Bottom-Up and Top-Down: Recent Trends in FPGA Network-on-Chip Design

Assistant Professor Nachiket Kapre, University of Waterloo
Chaired by
Dr MITRA, Tulika, Professor, School of Computing

  14 Jan 2019 Monday, 02:00 PM to 03:00 PM

 Executive Classroom, COM2-04-02


In this talk, I will discuss recent and active research projects at the University of Waterloo's Configurable Architectures Group (WatCAG).

1. LegUp-NoC integrates the Hoplite FPGA Network-on-Chip with the LegUp High-Level synthesis tool and uses it for parallelizing loops with indirect addressing. These programming patterns are notoriously difficult to accelerate, and occur in various workloads such as sparse matrix operations, graph operations, FFTs, sorting, among others. The work was presented at FCCM 2018 and was led by Waterloo undergrad Asif Islam

2. Fast-Track FPGA Interconnect proposal leverages the segmented nature of modern FPGA interconnect to provide fast traversal paths for packet-switched FPGA NoC packets. This allows us to exploit FPGA interconnect properties to deliver throughput and latency wins for deflection routed NoCs. This work was presented at ISCA 2018 and was a result of a collaboration with Prof. Tushar Krishna at Georgia Tech.


Nachiket Kapre is an Assistant Professor in the Department of Electrical and Computer Engineering at University of Waterloo, Canada. He was previously an Assistant Professor at Nanyang Technological University, Singapore in the School of Computer Engineering. He has received his M.S in Electrical Engineering (2005) and Computer Science (2006) and a PhD in Computer Science (2010) from California Institute of Technology, Pasadena. He is primarily interested in understanding and exploiting the potential of parallel, spatial architectures such as FPGAs for energy-efficient computing. His research has won best paper awards at FPT 2011, FPL 2015, CASES 2016, and TRETS 2017.