Changing the Computer Performance Locomotive, from Process Technology to Computer Architecture
08 Nov 2018 Thursday, 10:00 AM to 11:00 AM
COM1 Level 2
SR3, COM1-02-12 NB: Refreshments will be provided after the talk.
For the last 40 years, Process Technology and Computer Architecture were orchestrating the magnificent computing performance growth. However, Process Technology was the main locomotive, while Computer Architecture contributed to only about a 1/3 of the performance outcome. It seems that we have reached a major turning point; Moore's law is reaching its end, while Dennard scaling ended already, while all along performance requirements continue to soar in many new exciting applications. In order to continue moving the performance train, the only existing viable engine is Computer Architecture. In this talk, we will present some of our conceptual research directions that may open new architectural avenues, mainly in the Heterogeneous computing domain. We will also show examples of a Neural Network approach.
Uri Weiser is a Professor Emeritus at the Electrical Engineering department, the Technion IIT and is technically involved in numerous startups. He received his bachelor and master degrees in EE from the Technion and Ph.D in CS from the University of Utah, Salt Lake City. Professor Weiser worked at Intel from 1988-2006. At Intel, Weiser initiated the definition of the Pentium(R) processor, drove the definition of Intel's MMX(TM) technology, invented the Trace Cache, co-managed the a new Intel Microprocessor Design Center at Austin, Texas and formed an Advanced Media applications research activity. Weiser was appointed an Intel Fellow in 1996, in 2002 he became an IEEE Fellow and in 2005 an ACM Fellow and got the IEEE/ACM Eckert Mauchly award in 2016.
Prior to his career at Intel, Professor Weiser worked for the Israeli Department of Defense as a research system engineer and later with National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor. Professor Weiser was an Associate Editor of IEEEMicro Magazine and Computer Architecture Letters and served in numerous ACM/IEEE committees.