Solving the DRAM Scaling Challenge
University of Virginia (UVa)
COM2 Level 4
Executive Classroom, COM2-04-02
Technology scaling of DRAM cells has enabled higher capacity memory for the last few decades. Unfortunately, DRAM cells become vulnerable to failure as they scale down to a smaller size. Enabling high-performance, energy-efficient, scalable memory systems without sacrificing the reliability is a major research challenge. My work focuses on designing a scalable memory system by rethinking the traditional assumptions in abstraction and separation of responsibilities across system layers.
In this talk, I will discuss three fundamental ways to enable DRAM scaling. First, we can enable scaling by letting the manufacturers build smaller cells without providing any strict reliability guarantee. I envision manufacturers shipping DRAMs without fully ensuring correct operation, and the system being responsible for detecting and mitigating DRAM failures while operating in the field. However, designing such a system is difficult due to intermittent DRAM failures. In this talk, I will discuss a system design, capable of providing reliability guarantees even in the presence of intermittent failures. Second, we can enable high-capacity memory leveraging the emerging non-volatile memory technologies that are predicted to be more scalable. I will present my vision to redefine the hardware and operating system interface to unify memory and storage system with non-volatile memory and discuss the opportunities and challenges of such a system. Third, tolerating failures in the application can improve memory scalability. The fundamental challenge of such a system is how to assure, verify, and quantify the quality of the results. I envision a system that limits the impact of memory failures such that it is possible to statically determine the worst-case results from the maximum possible error in the input.
Samira Khan is an Assistant Professor at the University of Virginia (UVa). Prior to joining UVa, she was a Post Doctoral Researcher at Carnegie Mellon University, funded by Intel Labs. Her research focuses on improving the performance, efficiency, and reliability of the memory system. She is the recipient of NSF CRII Award, NSF GOALI Award, and Rising Stars in EECS Award. She received her PhD from the University of Texas at San Antonio. During her graduate studies, she worked at Intel, AMD, and EPFL.