The P4 packet processing language, and its use for high-speed networking based on FPGA technology
Xilinx Labs, San Jose, USA
07 Dec 2017 Thursday, 02:00 PM to 03:30 PM
COM1 Level 2
Video Conference Room, COM1-02-13
P4 is a new high-level programming language for packet processing, which abstracts away implementation detail. This talk will cover the brief history of P4, and the main features of the language. It will focus on an implementation for high-speed (100Gb/s range) networking on Xilinx FPGAs, which forms the basis for the Xilinx SDNet development environment. Two recent applications, to NFV service function chaining, and to inband network telemetry, will be described. The talk will also overview two current research projects involving putative P4 extensions and their FPGA implementation: one involving programmable packet processing architectures (work with Stanford), the other involving programmable traffic management (work with MIT, NYU and Stanford). Finally, the new open P4->NetFPGA workflow for networking researchers will be briefly introduced.
Professor Gordon Brebner is a Distinguished Engineer at Xilinx, Inc., the world's leading provider of all-programmable FPGAs and SoCs. He works in Xilinx Labs, leading an international group researching issues surrounding networked processing systems of the future. His main personal research interests concern dynamically configurable architectures, domain-specific languages with highly concurrent implementations, and scalable-performance programmable networking and edge computing systems. Most recently, his research has led to the Xilinx SDNet product for P4-programmed SDN, IBN and NFV at 100G+ rates. Prior to joining Xilinx in 2002, he was the Professor of Computer Systems and Head of the Department of Computer Science at the University of Edinburgh. He is currently co-chair of the P4 Language Design working group in the P4 Language Consortium (P4.org).