CS SEMINAR

SiLago: The Next Generation Synchorous VLSI Design Platform

Speaker
Professor Ahmed Hemani
Dept. of Electronics and Embedded Systems, School of ICT, KTH, Kista, Sweden
hemani@kth.se

Chaired by
Dr MITRA, Tulika, Professor, School of Computing
  tulika@comp.nus.edu.sg

  13 Oct 2017 Friday, 10:00 AM to 11:00 AM

 Video Conference Room, COM1-02-13


Abstract: VLSI design community faces the challenge of unscalable large engineering and manufacturing costs and 2-4 orders loss in computational efficiency compared to hardwired solutions. As a solution, SiLago raises the abstraction of physical design platform from the present day boolean level standard cells to micro-architectural level SiLago (Silicon Large Grain Objects) blocks as the atomic physical design building blocks and introduce a grid based synchorous VLSI Design scheme to compose arbitrary designs by abutting SiLago blocks to eliminate the logic and physical syntheses for the end user. The word synchorous is derived from the Greek word for space - choros. Synchorous objects discretize space uniformly with the grid, the way synchronous objects discretize time with clock ticks. The synchoros design style and micro-architectural level physical design enables SiLago method to rapidly explore the higher abstraction design space and generate valid VLSI designs at GDSII level corresponding 10-100 million gate complexity in minutes with an engineering effort comparable to programming. The SiLago method also holds the promise to eliminate the mask engineering cost.

Biodata: Ahmed Hemani is Professor in Electronic Systems Design at School of ICT, KTH, Kista, Sweden. His current areas of research interests are massively parallel architectures and design methods and their applications to scientific computing and autonomous embedded systems inspired by brain. In past he has contributed to high-level synthesis - his doctoral thesis was the basis for the first high-level synthesis product introduced by Cadence called visual architect. He has also pioneered the Networks-on-chip concept and has contributed to clocking and low power architectures and design methods. He has extensively worked in industry including National Semiconductors, ABB, Ericsson, Philips Semiconductors, Newlogic. He has also been part of three start-ups.